A novel technique for low-power D/A conversion based on PAPR reduction.

Theodoros Giannopoulos Vassilis Paliouras

Published in: ISCAS (2006)

Keyphrases

low power
power consumption
low cost
high speed
power reduction
high power
single chip
vlsi architecture
low power consumption
wireless transmission
image processing
logic circuits
gate array
vlsi circuits
high capacity
cmos technology
digital signal processing