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Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.

L. F. FullerC. Kraaijenvanger
Published in: Great Lakes Symposium on VLSI (1995)
Keyphrases
  • gate array
  • low power
  • high speed
  • circuit design
  • single chip
  • case study
  • manufacturing process
  • low cost
  • power consumption
  • digital signal processing
  • cmos technology