Graphene Research in 200 mm CMOS Pilot Line.

M. Lukosius R. Lukose Marco Lisker G. Luongo M. Elviretti Andreas Mai Christian Wenger

Published in: MIPRO (2022)

Keyphrases

cross section
low cost
high speed
line segments
power consumption
analog vlsi
circuit design
average error
power supply
neural network
low power
rms error
production line
single chip
line drawings
low voltage
delay insensitive
image processing