Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit.
Zafar TakhirovBobak NazerAjay JoshiPublished in: ISQED (2012)
Keyphrases
- circuit design
- logic synthesis
- digital circuits
- delay insensitive
- logic circuits
- error rate
- high speed
- modal logic
- multi valued
- micron cmos
- classical logic
- chip design
- electronic circuits
- user feedback
- risk management
- error bounds
- digital media
- error analysis
- contrast enhancement
- predicate logic
- asynchronous circuits
- proof theory
- digital libraries
- analog vlsi
- decision feedback
- data sets