Low-power design of decimation filters for a digital IF receiver.
Brian A. WhiteMohamed I. ElmasryPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2000)
Keyphrases
- low power
- mixed signal
- power consumption
- single chip
- vlsi architecture
- high speed
- low cost
- low power consumption
- logic circuits
- power dissipation
- cmos technology
- digital signal processing
- multi channel
- gate array
- power reduction
- vlsi circuits
- cmos image sensor
- image sensor
- ultra low power
- analog to digital converter
- nm technology
- power saving
- design process