A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure.
To-Po WangShih-Hua ChiangPublished in: SoCC (2015)
Keyphrases
- low power
- low power consumption
- power consumption
- high speed
- low cost
- cmos technology
- single chip
- high noise
- vlsi circuits
- digital signal processing
- wireless transmission
- image sensor
- low signal to noise ratio
- energy dissipation
- vlsi architecture
- high power
- delay insensitive
- noise level
- wide dynamic range
- real time
- logic circuits
- low voltage
- cmos image sensor
- ultra low power
- noise model
- power reduction
- mixed signal
- hardware and software
- image restoration
- nm technology