A hierarchical parallel evolvable hardware based on network on chip.
Jun Rong WangDan WangJin-Mei LaiPublished in: ReConFig (2013)
Keyphrases
- evolvable hardware
- network on chip
- multi processor
- parallel processing
- packet switched
- evolutionary algorithm
- evolutionary computation
- fault tolerant
- interconnection networks
- bio inspired
- digital circuits
- routing algorithm
- single processor
- massively parallel
- adaptive systems
- distributed memory
- parallel implementation
- shared memory
- database
- latest developments
- power dissipation
- multi core processors
- genetic programming
- low cost
- data mining