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A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors.

Wenbo DaiHong AnQi LiGongming LiBobin DengShilei WuXiaomei LiYu Liu
Published in: ISPA (2011)
Keyphrases
  • network on chip
  • low cost
  • parallel implementation
  • neural network
  • levels of abstraction
  • high speed
  • operating system
  • message passing
  • shared memory
  • high density
  • single chip
  • multi processor