Live Demonstration: Neuromorphic Row-by-Row Multi-Convolution FPGA Processor-SpiNNaker Architecture for Dynamic-Vision Feature Extraction.
Ricardo Tapiador-MoralesJuan Pedro Dominguez-MoralesDaniel Gutierrez-GalanAntonio Rios-NavarroAngel Jiménez-FernandezAlejandro Linares-BarrancoPublished in: ISCAS (2019)
Keyphrases
- real time
- feature extraction
- parallel architecture
- image processing
- high speed
- xilinx virtex
- systolic array
- hardware implementation
- multi processor
- fpga device
- single chip
- low cost
- computer vision
- parallel processing
- signal processing
- wavelet transform
- feature vectors
- face recognition
- extracted features
- hardware architecture
- instruction set
- fpga implementation
- industry standard
- dedicated hardware
- computation intensive
- general purpose processors
- software implementation
- communication protocol
- hardware design
- computer architecture