Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips.
R. JayagowriK. S. GurumurthyPublished in: VDAT (2012)
Keyphrases
- low power
- high speed
- power dissipation
- cmos technology
- vlsi architecture
- chip design
- power consumption
- single chip
- vlsi circuits
- low cost
- flip flops
- gate array
- mixed signal
- signal processor
- high power
- digital signal processing
- wireless transmission
- logic circuits
- efficient implementation
- low power consumption
- low voltage
- image sensor
- power reduction
- vlsi implementation
- digital camera
- signal processing
- ultra low power