ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA.
Diogo ZandonaiSergio BampiMarcel BergermanPublished in: DIPES (2004)
Keyphrases
- hardware architecture
- motion estimation
- field programmable gate array
- hardware implementation
- pipelined architecture
- processing elements
- hardware architectures
- parallel computing
- fpga device
- xilinx virtex
- image processing algorithms
- parallel hardware
- parallel programming
- motion compensated
- reconfigurable hardware
- parallel architecture
- parallel processing
- motion compensation
- massively parallel
- video coding
- motion vectors
- efficient implementation
- signal processing
- early termination
- optical flow
- parallel architectures
- information systems
- image processing
- image sequences
- video sequences
- software engineering
- general purpose
- fine grained
- computing systems
- computer vision