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Variability-aware task mapping strategies for many-cores processor chips.
Fabien Chaix
Gilles Bizot
Michael Nicolaidis
Nacer-Eddine Zergainoh
Published in:
IOLTS (2011)
Keyphrases
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high speed
multi core processors
high end
processor core
ibm zenterprise
data sets
intra class
parallel architectures
general purpose processors
real time
neural network
integrated circuit
functional units
level parallelism
chip design