Variability-aware task mapping strategies for many-cores processor chips.

Fabien Chaix Gilles Bizot Michael Nicolaidis Nacer-Eddine Zergainoh

Published in: IOLTS (2011)

Keyphrases

high speed
multi core processors
high end
processor core
ibm zenterprise
data sets
intra class
parallel architectures
general purpose processors
real time
neural network
integrated circuit
functional units
level parallelism
chip design