A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder.
Yibo FanGenwei TangXiaoyang ZengPublished in: IEEE Access (2019)
Keyphrases
- vlsi architecture
- intra prediction
- mode decision
- avc intra
- pixel wise
- low complexity
- video coding standard
- low power
- video codec
- video coding
- coding efficiency
- distributed video coding
- power consumption
- video compression
- spatial correlation
- motion compensation
- rate distortion
- coding method
- computational complexity
- low cost
- high speed
- motion estimation
- vlsi implementation
- discrete cosine transform
- error concealment
- macroblock
- motion vectors
- video transmission
- motion compensated
- digital video
- bit rate
- pixel level
- real time
- background subtraction
- multiscale
- multiresolution
- bit plane
- block size
- spatial information
- image coding
- appearance model