High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology.

Deepon Saha Subir Kumar Sarkar

Published in: Microelectron. J. (2014)

Keyphrases

low power
cmos technology
high speed
power dissipation
power consumption
silicon on insulator

low cost
single chip
low voltage
nm technology
mixed signal
logic circuits

low power consumption
digital signal processing
image sensor
power reduction
embedded dram
gate array

real time
random access memory
cmos image sensor
leakage current
ultra low power