FPGA PUF Based on Programmable LUT Delays.
Bilal HabibKris GajJens-Peter KapsPublished in: DSD (2013)
Keyphrases
- single chip
- low cost
- digital signal processors
- field programmable gate array
- electronic devices
- general purpose processors
- hardware implementation
- real time image processing
- high speed
- low power
- general purpose
- inverse halftoning
- hardware design
- programmable logic
- lookup table
- data acquisition
- hardware architecture
- hardware architectures
- digital signal
- software implementation
- pipelined architecture
- verilog hdl
- fpga implementation
- neural network
- dedicated hardware
- image sensor
- fpga device
- data flow
- systolic array
- efficient implementation
- gray scale
- signal processor
- image quality
- image data