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0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI.

Takahiro WatanabeMinoru Watanabe
Published in: ISVLSI (2012)
Keyphrases
  • gate array
  • low cost
  • signal processing
  • process model
  • hardware implementation
  • real world
  • artificial neural networks
  • development process