A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS.
Rei SumikawaKota ShibaAtsutake KosugeMototsugu HamadaTadahiro KurodaPublished in: ASP-DAC (2023)
Keyphrases
- delay insensitive
- high speed
- pattern recognition
- classification accuracy
- asynchronous circuits
- multi valued
- support vector
- machine learning
- feature vectors
- support vector machine
- low power
- parallel processing
- sound and complete axiomatization
- chip design
- random access memory
- text classification
- feature extraction
- decision trees
- feature selection
- logic programming
- support vector machine svm
- image classification
- feature set
- dct coefficients
- low cost
- single chip
- training set
- neural network