Low power heterogeneous 3D Networks-on-Chip architectures.
Michael Opoku AgyemanAli AhmadiniaAlireza ShahrabiPublished in: HPCS (2011)
Keyphrases
- low power
- high speed
- low cost
- single chip
- low power consumption
- mixed signal
- cmos technology
- power consumption
- power dissipation
- signal processor
- image sensor
- high power
- ultra low power
- digital signal processing
- power reduction
- vlsi circuits
- wireless transmission
- network structure
- logic circuits
- vlsi architecture
- cmos image sensor
- nm technology
- real time
- high density
- digital camera
- delay insensitive
- design process
- gate array