ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.

Ming-Dou Ker Tung-Yang Chen Chung-Yu Win

Published in: ISCAS (4) (2001)

Keyphrases

cmos technology
low power
power dissipation
power consumption
spl times
low voltage
design process
efficient implementation
case study
design methodology
design considerations
integrated circuit
mixed signal
image sensor
parallel processing
high speed
low cost