Formal verification of behavioral VHDL specifications: a case study.
Felix NicoliLaurence PierrePublished in: EURO-DAC (1994)
Keyphrases
- formal verification
- model checker
- bounded model checking
- automated verification
- model checking
- symbolic model checking
- case study
- hardware implementation
- formal specification
- functional verification
- program slicing
- test bed
- integrated circuit
- artificial intelligence
- knowledge base
- formal methods
- human behavior
- transition systems
- temporal logic
- software engineering
- reinforcement learning