A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC.
Siddharth DevarajanLarry SingerDan KellySteven DeckerAbhishek KamathPaul WilkinsPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- analog to digital converter
- power consumption
- signal to noise ratio
- low power
- power supply
- hd video
- image sensor
- noise reduction
- processing pipeline
- random access memory
- nm technology
- cmos image sensor
- mixed signal
- database
- edge detection
- pipeline architecture
- sampling rate
- signal noise ratio
- circuit design
- modulation scheme
- dynamic range
- power plant
- image compression