FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction.
Yi CaiWeiming WangWeifeng QianJia XingKai TaoJunjie YinShihua ZhangMing LeiErkun SunKe YangHungchang ChienQun LiaoHuan ChenPublished in: OFC (2018)
Keyphrases
- forward error correction
- error propagation
- packet loss
- error resilient
- wireless channels
- feature vectors
- channel coding
- high speed
- rate allocation
- bit errors
- error resilience
- error detection
- error recovery
- unequal error protection
- network conditions
- error correction
- bitstream
- reed solomon codes
- video transmission
- video streams
- packet losses
- low cost
- application layer
- real time
- optical flow