Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator.
Antonio Rios-NavarroRicardo Tapiador-MoralesAngel Jiménez-FernandezManuel Domínguez-MoralesClaudio AmayaAlejandro Linares-BarrancoPublished in: CoRR (2018)
Keyphrases
- hw sw
- hardware software partitioning
- embedded systems
- hardware software co design
- hardware software
- field programmable gate array
- hardware and software
- design methodology
- low cost
- hardware implementation
- object oriented
- grid computing
- feature analysis
- parallel computing
- real time
- signal processing
- sensor networks
- fuzzy logic