Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis.
Eduardo Ribeiro da SilvaF. CostaFrank Herman BehrensRemerson Stein KickhofelRicardo MaltionePublished in: LATW (2009)
Keyphrases
- small size
- vlsi architecture
- real time
- test data generation
- mobile devices
- high speed
- software architecture
- network architecture
- management system
- fixed size
- computational complexity
- sigma delta
- analog vlsi
- ubiquitous environment
- network infrastructure
- internal and external
- software testing
- low power
- embedded systems
- distributed architecture
- network services
- remote control
- small sized
- test cases