Automatic generation of FPGA hardware accelerators using a domain specific language.
Ricardo MenottiJoão M. P. CardosoMarcio Merino FernandesEduardo MarquesPublished in: FPL (2009)
Keyphrases
- field programmable gate array
- automatically generate
- hardware implementation
- low cost
- high speed
- verilog hdl
- fpga implementation
- real time image processing
- gate array
- hardware design
- signal processing
- hardware architecture
- real time
- systolic array
- digital signal
- software implementation
- single chip
- low power consumption
- website
- hardware architectures
- pattern recognition
- computer vision
- feature selection
- neural network
- efficient implementation
- fpga hardware
- optimal solution
- data structure