Gate oxide enhancement for whole chip ESD design between different power domains.

Hongwei Li Guang Chen Huijuan Cheng

Published in: ASICON (2013)

Keyphrases

chip design
user interface
physical design
nm technology
circuit design
single chip
ibm power processor
design process
neural network
low cost
functional verification
power consumption
cmos technology
design considerations
low power
image enhancement
high speed
real world