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Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.
Avinash Karanth Kodi
Ashwini Sarathy
Ahmed Louri
Published in:
IEEE Trans. Computers (2008)
Keyphrases
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interconnection networks
power allocation
ibm power processor
low cost
multistage
routing algorithm
network on chip
high speed
parallel algorithm
fault tolerant
power consumption
message passing
power dissipation