Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Massimo AliotoGiuseppe Di CataldoGaetano PalumboPublished in: Microelectron. J. (2007)
Keyphrases
- low power
- logic circuits
- power dissipation
- low power consumption
- signal processor
- power consumption
- low cost
- high speed
- single chip
- vlsi circuits
- high power
- cmos technology
- power reduction
- digital signal processing
- gate array
- wireless transmission
- delay insensitive
- vlsi architecture
- mixed signal
- nm technology
- image sensor
- distributed memory
- wireless networks