Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications.
Tam-Anh ChuPublished in: ICCD (1992)
Keyphrases
- finite state machines
- model checking
- asynchronous circuits
- delay insensitive
- digital circuits
- high level synthesis
- automated verification
- formal verification
- model checker
- formal specification
- analog circuits
- state machine
- temporal logic
- finite state automata
- semi automatic
- control system
- concurrent systems
- logic synthesis
- functional decomposition
- state transition
- bounded model checking
- hidden markov models
- power dissipation
- relational databases
- circuit design
- information extraction