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A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology.
Souradip Sen
Utkarsh Upadhyaya
Krishna Reddy Kondreddy
Arun Goyal
Sandeep Goyal
Shalabh Gupta
Published in:
VLSI Design (2021)
Keyphrases
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cmos technology
mixed signal
low power
power consumption
spl times
parallel processing
low voltage
silicon on insulator
power dissipation
cmos image sensor
low cost
high speed
computer vision
image sensor
digital signal processing
hidden markov models
data flow
multi channel
pattern recognition