Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC.
Yang SongZhenyu LiuSatoshi GotoTakeshi IkenagaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
- variable block size
- motion estimation
- vlsi architecture
- low complexity
- motion estimator
- mode decision
- inter frame
- intra prediction
- vlsi implementation
- motion compensation
- motion vectors
- video coding
- multiple reference frames
- variable block size motion estimation
- video compression
- motion compensated
- low power
- video sequences
- image sequences
- coding efficiency
- rate distortion
- motion field
- video coding standard
- quadtree
- optical flow
- computational complexity
- computer vision
- motion model
- scalable video coding
- block matching
- reference frame
- spatial domain
- motion estimation algorithm
- block size
- macroblock
- bit plane
- video codec
- spatial correlation
- multiscale
- temporal correlation
- distributed video coding
- prediction error