Reducing parity generation latency through input value aware circuits.

Yusuf Osmanlioglu Yusuf Onur Koçberber Oguz Ergin

Published in: ACM Great Lakes Symposium on VLSI (2009)

Keyphrases

digital circuits
data sets
error correction
input data
artificial intelligence
search engine
image sequences
evolutionary algorithm
response time
high speed
genetic algorithm
neural network
significantly reduced
generation process
low latency
real time
input patterns
analog circuits
power reduction
analog vlsi