Corrections to "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects".
Hyungmin ChoPublished in: IEEE Access (2019)
Keyphrases
- instruction set
- level parallelism
- floating point
- application specific
- interaction effects
- negative effects
- individual differences
- anecdotal evidence
- negative impact
- computer architecture
- positive effects
- error rate
- error detection
- processor core
- statistically significant
- multi core processors
- high speed
- error analysis
- estimation error
- embedded systems
- measurement error
- parallel processing
- error bounds
- computation intensive
- instruction set architecture
- memory subsystem
- parallel architectures
- multicore processors
- real time
- general purpose