ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors.
Dhruv GajariaTosiron AdegbijaPublished in: MEMSYS (2019)
Keyphrases
- energy efficient
- multicore processors
- computing power
- wireless sensor networks
- energy consumption
- operating system
- highly parallel
- sensor networks
- parallel algorithm
- parallel architectures
- routing protocol
- data dissemination
- memory access
- base station
- energy efficiency
- computing systems
- data transmission
- power reduction
- parallel programming
- routing algorithm
- massively parallel
- sensor nodes
- shared memory
- embedded systems
- main memory
- low cost