A design of ternary logic circuits using M-NAND and NOT gates.

Akio Odaka Kunio Satoh

Published in: Systems and Computers in Japan (1985)

Keyphrases

logic circuits
low power
functional decomposition
gate array
power dissipation
tunnel diode
logic synthesis
low power consumption
power consumption
user interface
embedded systems
real time
design process
signal processing
high speed
pattern recognition
case study