A parallel algorithm for constructing reduced visibility graph and its FPGA implementation.
K. SridharanT. K. PriyaPublished in: J. Syst. Archit. (2004)
Keyphrases
- parallel algorithm
- fpga implementation
- hardware implementation
- parallel computation
- parallel programming
- cluster of workstations
- parallel version
- binary search trees
- medial axis transform
- discovery of association rules
- shared memory
- transfer function
- image processing algorithms
- field programmable gate array
- multiscale
- depth first search
- efficient implementation