FPGA architecture for pairwise statistical significance estimation.
Daniel HonboAmit PandeAlok N. ChoudharyPublished in: Int. J. High Perform. Syst. Archit. (2013)
Keyphrases
- statistical significance
- pairwise
- statistically significant
- hardware implementation
- hardware architecture
- statistical tests
- hardware design
- high speed
- information retrieval
- similarity measure
- fpga technology
- binding sites
- loss function
- low cost
- permutation tests
- parameter estimation
- gene sets
- learning styles
- null hypothesis
- reconfigurable hardware
- pipelined architecture