Python-based DSL for generating Verilog model of Synchronous Digital Circuits.

Mandar Datar Dhruva S. Hegde Vendra Durga Prasad Manish Prajapati Neralla Manikanta Devansh Gupta Janampalli Pavanija Pratyush Pare Akash Shivam Gupta Sachin B. Patkar

Published in: CoRR (2024)

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