Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM.
Changkun WuWei ZhangQi JiaYanyan LiuPublished in: IET Image Process. (2017)
Keyphrases
- hardware architecture
- hardware implementation
- low cost
- vlsi implementation
- host computer
- real time
- memory subsystem
- design considerations
- memory access
- programmable logic
- high speed
- multithreading
- circuit design
- high density
- software implementation
- efficient implementation
- processing units
- hardware design
- wavelet transformation
- hardware and software
- analog vlsi
- ibm zenterprise