Low-Power Multiplier Design Using a Bypassing Technique.

Chua-Chin Wang Gang-Neng Sung

Published in: J. Signal Process. Syst. (2009)

Keyphrases

low power
low power consumption
single chip
low cost
power consumption
high speed

vlsi architecture
logic circuits
cmos technology
digital signal processing
gate array

power dissipation
ultra low power
vlsi circuits
power reduction
hardware and software

embedded systems
high power
digital camera
mixed signal
cmos image sensor