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Compiling VHDL into a high-level synthesis design representation.

Petru ElesKrzysztof KuchcinskiZebo PengMarius Minea
Published in: EURO-DAC (1992)
Keyphrases
  • high level synthesis
  • case study
  • circuit design
  • hardware design
  • pairwise
  • design process
  • computer aided
  • parallel architecture