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A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s.
Kejun Wu
Yangchen Xie
Shubo Tao
Zhong Zhang
Ning Ning
Jing Li
Qi Yu
Published in:
Microelectron. J. (2023)
Keyphrases
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sampling rate
high speed
frame rate
duty cycle
power consumption
clock gating
low power
clock frequency
root mean square
real time
packet loss
feature selection
three dimensional
circuit design
analog circuits
interval type fuzzy sets