A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL.
Lorenzo Di TucciDavide ConficconiAlessandro ComodiSteven A. HofmeyrDavid DonofrioMarco D. SantambrogioPublished in: IPDPS Workshops (2018)
Keyphrases
- computational power
- energy efficient
- hardware architectures
- hardware architecture
- parallel processing
- multi core architecture
- wireless sensor networks
- energy consumption
- hardware implementation
- processing elements
- sensor networks
- field programmable gate array
- base station
- energy efficiency
- parallel programming
- routing protocol
- parallel architectures
- parallel computing
- xilinx virtex
- computer architecture
- distributed memory
- parallel architecture
- image processing algorithms
- parallel implementation
- embedded systems
- multi core processors
- routing algorithm
- shared memory