Variable-Latency Floating-Point Multipliers for Low-Power Applications.
Shiann-Rong KuangJiun-Ping WangHong-Yi HuangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
- low power
- floating point
- power consumption
- low cost
- high speed
- single chip
- fixed point
- memory bandwidth
- vlsi architecture
- low power consumption
- instruction set
- cmos technology
- sparse matrices
- power reduction
- mixed signal
- vlsi circuits
- digital signal processing
- floating point arithmetic
- gate array
- image sensor
- power dissipation
- image processing
- decision variables
- constraint programming
- pairwise