A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling.

Mohammad Fattah Soodeh Aghli Moghaddam Siamak Mohammadi

Published in: DSD (2009)

Keyphrases

delay insensitive
asynchronous circuits
high speed
low cost
low power
analog vlsi
high density
risk assessment
programmable logic
learning phase
link structure
vlsi design
preprocessing phase
single chip
neural network
training phase
evolutionary algorithm