Fast and Robust Face Detection on a Parallel Optimized Architecture Implemented on FPGA.
Nicolas FarrugiaFranck MamaletSébastien RouxFan YangMichel PaindavoinePublished in: IEEE Trans. Circuits Syst. Video Technol. (2009)
Keyphrases
- pipelined architecture
- hardware implementation
- robust face detection
- field programmable gate array
- parallel architecture
- fpga device
- face detection
- systolic array
- hardware design
- hardware architecture
- parallel processing
- fpga hardware
- face authentication
- reconfigurable hardware
- processing elements
- fpga implementation
- parallel computers
- parallel computing
- parallel hardware
- xilinx virtex
- shared memory
- embedded systems
- multi class
- hardware software
- distributed memory
- level parallelism
- color images