High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.
Vili ViitamäkiPanu SjovallJarno VanneTimo D. HämäläinenPublished in: ISCAS (2017)
Keyphrases
- high level
- low power
- video codec
- low complexity
- low power consumption
- hardware implementation
- discrete cosine transform
- video encoder
- power consumption
- high speed
- hardware architecture
- low level
- low cost
- video coding
- motion estimation
- video compression
- low bit rate
- dct domain
- processing capabilities
- single chip
- computer vision
- image compression
- signal processing