FPGA automatic re-synchronisation for pipelined, floating point control systems applications.

Beniamin Apopei Tony J. Dodd

Published in: Des. Autom. Embed. Syst. (2011)

Keyphrases

floating point
control system
fixed point
square root
sparse matrices
bayesian networks
low cost
parallel architecture
instruction set
real time
image processing
hardware implementation
data flow
field programmable gate array
floating point arithmetic