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Detecting errors in digital communications with CRC codes implemented with FPGA.

Constantin AntonLaurentiu IonescuIon TutanescuAlin MazareGheorghe Serban
Published in: ICITST (2009)
Keyphrases
  • pipelined architecture
  • low cost
  • high speed
  • error correction
  • real time image processing
  • real time
  • data sets
  • communication networks
  • error detection
  • fpga device
  • field programmable gate array
  • hardware design