Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems.
P. NagarajanN. Ashok KumarP. Venkat RamanaPublished in: Int. J. Wavelets Multiresolution Inf. Process. (2020)
Keyphrases
- low power
- high speed
- power dissipation
- single chip
- power consumption
- cmos technology
- low cost
- vlsi architecture
- low power consumption
- logic circuits
- power reduction
- high power
- digital signal processing
- gate array
- ultra low power
- nm technology
- circuit design
- mixed signal
- wireless transmission
- vlsi circuits
- flip flops
- image sensor
- signal processor
- design methodology
- computing systems
- embedded systems
- pattern recognition
- design process
- real time